Certain embodiments of the invention relate to the communication of data and control signals. More specifically, certain embodiments of the invention relate to a method and system for a transceiver bus.
Communication systems such as embedded systems and/or multiprocessor systems may often have a large component count dependent on their functionality. In general, the greater the number of components the greater the number of data, address and/or controls lines that must be provided to control the components. Furthermore, additional devices such as multiplexers and decoders may be required to provide interconnectivity between devices wishing to communicate with each other. The address, data, and control lines along with the wiring required for additional devices may result in extensive wiring for a printed circuit board (PCB) or core. In some instances, using several layers on a PCB may help to alleviate the problem of excessive wiring. Although, it may be expensive to fabricate multi-layered PCBs, the use of multi-layered PCBs and excessive wiring may also pose certain other problems. For example, excessive wiring may result in electromagnetic interference and/or electrostatic discharge. Accordingly, a bus may be used to save cost and also eliminate and/or solve some of these problems.
A bus is a device interface having one or more conductors or optical fibers that may serve as a common connection for a plurality of devices connected thereto. The bus may be configured to provide intra-device communication to devices located on the bus or inter-device communication to other devices residing on other inter-connected communication buses. For example, a time division multiplexing (TDM) bus consists of a plurality of conductors in which signals are communicated over the time division multiplexed bus in a channelized manner called a timeslot. In this regard, a carrier signal communicated by the bus may be divided in a plurality predefined individual channels. Each time slot is a channel defined by a unique time interval in which data may be communicated on the bus. Each device located or connected to the bus may be assigned one or more of a unique time slot in which to communicate over the bus. Accordingly, dependent on a size of the bus, at least some or all of the devices connected to the bus may simultaneously communicate over the TDM bus. Although time division multiplexed buses may permit simultaneous device communication, they may be expensive to implement and are preferably employed in medium too large scale communication systems.
One less expensive alternative to a time division multiplexed bus is an inter-integrated circuit (IIC or I2C) bus. The I2C bus is a serial interface that may be adapted to connect one or more communication devices coupled to the I2C bus. The I2C bus conforms to certain standards and specification that describe the protocols, signals and data formats, which are necessary for devices connected to the bus to communicate. The I2C bus has two (2) wire conductors, namely a first wire conductor, which may carry a serial data (SDA) signal, and a second wire conductor, which may carry a serial clock (SCL) signal. Each device connected to the I2C bus may require a unique address and may be configured to dynamically operate in either a master and/or slave communication mode. The mode of operation of a device may be dependent on its data transfer status.
FIG. 1 is a block diagram 100 of an exemplary I2C bus 120. Referring to FIG. 1, there is shown a bus controller 102, a plurality of devices 104, 106, 108, 110, a serial clock line (SCL) 114 and a serial data line (SDA) 116.
The bus controller 102 may be any suitable microprocessor, microcontroller or suitable specialized processor that may be adapted to control the communication of signals such as SCL 114 and SDA 116 over bus 120.
The devices 104, 106, 108, 110, may be any suitable device that may be connected to the bus 120. For example, devices 104, 106, 108, 110 may be a memory, a field programmable gate array (FPGA), a SoC (System On a Chip), an application specific integrated circuit (ASIC), a video controller, an audio controller, an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC). Any of the devices 104, 106, 108, 110 may be adapted to operate in a master and/or slave mode. A device that may initiate a data transfer and generate one or more clock signals may be referred to a master device. Additionally, a device that may be adapted to receive data from a master device may be referred to as a slave device. In this regard, a master device may be adapted to operate as a slave when it receives data from another master device. Accordingly, a status of a device as a master device or a slave device may adaptively change during operation.
The SCL line 114 and the SDA 116 lines may be connected to a positive power supply, for example a +5V supply, which is driven by open collector drivers. In this regard, +5V may represent logic one (0) and a ground or 0V may represent a logic zero (0). Each of the devices 104, 106, 108, 110 are connected to the SDA line 116 and the SCL line 114 through a pull up resistor. In operation, the SCL signal on the SCL line 114 and SDA signal on the SDA line 116 remain logic one (1) or high unless driven to logic zero (0) or low by any one or more of the devices 104, 106, 108, 110. Since the SDA line 116 and the SCL line 114 are wired as an “AND” function, the signals on these lines will be logic one (1) or high if all the devices on bus 120 drive these signals at a logic one (1) or high.
The SDA line carries data values for one or more of the devices 104, 106, 108, 110. Accordingly, any one or more of the devices 104, 106, 108, 110 wishing to operate in a master mode should have the capability to drive and sense both the SCL signal on the SCL line 114 and SDA signal on the SDA line 116. Although any one or more of the devices 104, 106, 108, 110, may wish to operate as a master on the bus 120, a special arbitration sequence will be followed and only one of the devices will prevail and become a master on the bus 120 at any given instant. The SCL line 114 and SDA line 116 may be configured as bi-directional communication lines that may be suitable for communicating both the SCL clock signal and SDA data signal respectively in both directions along bus 120.
The I2C bus utilizes a predefined data transfer format. FIG. 2a is a diagram 200 of a data transfer format for an I2C bus operating in normal mode. Referring to FIG. 2, there is shown a start condition (S) 204, address (ADDR) 212, a read/write bit 214, an acknowledge (ACK) bit 216, a data byte 218, an ACK bit 220, a data byte 222, an ACK bit 224, a data byte 226, an ACK bit 228 and a stop bit 230.
The start condition (S) 204 is part of a start of communication procedure and may be used to initiate communication over bus 120. The first byte following the start condition (S) 204 contains the 7-bit address field (ADDR) 212 followed by a 1-bit read/write bit 214. The address field (ADDR) 212 specifies the unique address of the device that is being communicated with or the addressed device.
The read/write bit 214 specifies whether an operation is a read or a write operation. When the read/write bit 214 is logic one (1), this may signify a write operation in which the master may be adapted to operate in receive mode and the slave in transmit mode. When the read/write bit 214 is logic zero (0), this may signify a write operation in which the master may be adapted to operate in transmit mode and the slave in receive mode.
The acknowledge (ACK) bit 216 follows the read/write bit 214 and specifies the response from a device that has the corresponding ADDR 212 or the addressed device. In this regard, the ACK bit 216 acknowledges receipt of the last byte of received data. The data byte 218 may represent actual data being communicated followed by a corresponding acknowledgement (ACK) bit 220. Similarly, the data byte 222 may represent actual data being communicated followed by a corresponding acknowledgement (ACK) bit 224. The final data byte 226 may be followed by ACK bit 228. The stop bit (P) 230 which may signify the end of a transaction for a communication session may follow the ACK bit 228. In general, the stop bit (P) 230 follows the last acknowledgement (ACK) corresponding to the last data byte communicated over the bus 120 by a device.
Since any of the devices 104, 106, 108, 110, may operate in either a master and/or a slave mode, there are four possible operational modes. These modes of operation include the master device acting as a transmitter, the master device acting as a receiver, the slave device acting as a transmitter and the slave device acting as a receiver. In a case where the master device may be adapted to operate as a transmitter, the master device may generate the start condition (S) 204, the stop condition (P) 230 and the clock signal on the SCL line 114. Since the master device operates as the transmitter, it may write data to the SDA line 116. In a case where the master device may be adapted to operate as a receiver, the master device may generate the start condition (S) 204, the stop condition (P) 230 and the clock signal on the SCL line 114. Since the master device operates as the receiver, it may read data bytes from the SDA line 116 and accordingly generate the appropriate ACK signals to acknowledge receipt of the read data bytes.
In a case where the slave device may be adapted to operate as a transmitter, the slave device may write data to the SDA line 116. However, the slave device may have the capability to stretch any clock signals that are on the CLK line (SCL) 114 to achieve synchronization. Particularly, when the slave device operates as a transmitter, it may extend or stretch any low clock periods. Finally, in a case where the slave device may be adapted to operate as a receiver, the slave device may read data from the SDA line 116 and generate the appropriate ACK signals to acknowledge receipt of the read data bytes. Similarly, when the slave device operates as a receiver, it may extend or stretch any low clock periods to achieve synchronization.
FIG. 2b is a timing diagram 240 illustrating bit-level synchronization by a slave device. Referring to FIG. 2b, there is shown a serial data signal SDA (242), a serial clock signal (SCL) 244, a master device clock signal (CLKm) 246 and a slave device clock signal (CLKs) 248. A master device may generate the CLKm signal 246 requesting data from a slave device. In response the slave device operating as a receiver, may extend or stretch any low clock periods to achieve synchronization. In this regard, the slave device may achieve synchronization with the master device by stretching the CLKm signal 246 generated by the master device from time instant tm1 to time instant ts1. Similarly, the slave device may achieve synchronization with the master device by stretching the CLKm signal 246 generated by the master device from time instant tm2 to time instant ts2.
FIG. 2c is a timing diagram 240 illustrating byte-level synchronization by a slave device. Referring to FIG. 2c, there is shown a serial data signal (SDA) 262, a serial clock signal (SCL) 264, a master device clock signal (CLKm) 266 and a slave device clock signal (CLKs) 268. The serial data signal (SDA) 262 includes byte 0 followed by an acknowledgement (A) 270 and byte 1 followed by an acknowledgement (A) 272. A master device may generate the CLKm signal 266 requesting data from a slave device. In response, the slave device operating as a receiver, may extend or stretch any low clock periods to achieve synchronization. In this regard, the slave device may achieve synchronization with the master device by stretching the CLKm signal 266 generated by the master device from time instant tm1 to time instant ts1. Similarly, the slave device may achieve synchronization with the master device by stretching the CLKm signal 246 generated by the master device from time instant tm1 to time instant ts1.
Referring to FIG. 2a, in operation, a master device may initiate communication by writing the start condition (S) 204 on the data line 116 of bus 120. The start condition (S) may be followed by the unique 7-bit device address 212 of a receiver. The receiver may be adapted to be a slave device. The slave device may be configured to sense the SDA line 116 in order to detect its address on the bus 120. Upon detecting its address on the SDA line 116, the slave device may determine whether to read or write to the SDA line 116 based on the read/write bit 214. If the byte consisting of the 7-bit address field and the read/write bit is correctly received, the slave or receiver device may write the ACK 216 to the SDA line 116 to acknowledge receipt of the last received byte. If the read/write bit 214 is logic one (1), the slave is being requested to transmit data by placing the data to be transmitted on the SDA line 116. If the read/write bit 214 is logic zero (0), the slave is being requested to receive data from the data the SDA line 116 of data bus 120.
Subsequent to receiving the acknowledgement (ACK) 216 from the slave device, the master device may transmit a first byte of data 218. The data byte may be transmitted starting with the most significant bit (MSB) and ending with the least significant bit (LSB). Subsequent to receiving a corresponding acknowledgement (ACK) 220 from the slave device, the master device may then transmit a second data byte 222. The slave device will acknowledge data byte 222 with a corresponding acknowledgement (ACK) 224. The master device will continue to transmit data to the receiving slave device until the last data byte 226 is sent and acknowledged by the ACK 228. Upon receipt of the last ACK 228 sent by the receiving slave device, the transmitting master device sends a stop condition (P) 230 to terminate the transfer of data to the receiving slave device. The master may be configured to generate the stop condition (P) 230 by holding SCL at logic one (1) or high while toggling SDA from a logic zero (0) or low to a logic one (1) or high.
A device wishing to access bus 120 may not gain access to the bus 120 until the bus is in an idle state. In this regard, during a period between when a device sends a start condition 204 and a device sends a stop condition 230, another device may not make an attempt to gain control of bus 120. The I2C bus utilizes an arbitration mechanism to resolve contention for access to the bus 120. Any device residing on the bus 120 that may be adapted to generate a clock signal on SCL line 114 and which may initiate and terminate a data transfer may be referred to as a master device. Although any one or more of the device 104, 106, 108, 110, connected to bus 120 may be a master device, only one of these devices may be a master at any given time instant. Any device with which a master communicates maybe referred to as a slave device. Whenever two or more master devices attempt to gain access to the bus at the same time or when the bus is in use, the arbitration mechanism will determine which device has priority to access the bus 120.
In a case where two or more devices acting as masters attempt to gain access to the bus 120, the arbitration mechanism may grant access to a first device that generates a logic zero (0) or low on the SDA line 116 where a remaining portion of the other devices contending for the bus generate a logic one (1) or high. During arbitration, a master device may detect transmission by another master device on the SDA line 116 of bus 120 if during a logic one (1) or high, the master device outputs a logic one (1) and detects a logic zero (0) or low on the SDA line 116 of bus 120. In this case, the master device generating the logic one (1) may lose arbitration of the contention and will set the data output high in order to release SDA line 116. The losing device may subsequently attempt to gain access to the bus 120. The master device that is transmitting is the winning master device and will continue transmitting data on the SDA line 116 of the bus 120. It may be necessary for the losing device to determine the 7-bit address (ADDR) whenever the device loses arbitration. This might be particularly important in a case where arbitration occurs while the 7-bit address (ADDR) is on the SDA line 116 of bus 120 and the winning master device is addressing the losing device. If the losing device detects it own address in the bus when it loses arbitration, it must immediately switch to a slave receiving mode of operation.
FIG. 3 is a timing diagram 300 of an exemplary arbitration between two devices. Referring to FIG. 3, there is shown a serial clock signal 302, a serial data signal 304, an output signal for a first device (D1) 306 and an output signal for a second device (D2) 308. Devices D1 and D2 are two master devices contending for the bus 102. At time instant ta, the output of device D1 is logic one (1) or high and the output of device D2 is logic zero (0). Since the bus 120 is wired “AND,” and device D2 sends a logic zero (0), the contention will be arbitrated in favor of D2. D1 one will lose the arbitration since at time instant ta, the output of device D1 is logic zero (0) or low.
FIG. 4 is a diagram 400 of data transfer format for an I2C bus operating in low-speed mode. Referring to FIG. 4, there is shown a start condition (S) 404, a start byte 406, a dummy acknowledge bit (A) 408, a restart condition (Sr) 410, an address (ADDR) 412, a read/write bit 414, an acknowledge (ACK) bit 416, a data byte 418, an ACK bit 420, a data byte 422, an ACK bit 424, a data byte 426, an ACK bit 428 and a stop bit 330. The data transfer format for the low-speed operating mode may facilitate access to bus 120 bus by slower speed devices.
The start condition (S) 404 is part of a start of communication procedure and may be used to initiate communication over bus 120. The start condition (S) 404 may be similar to the start condition (S) 204 of FIG. 2a. The start byte 406 is 00000001 and signifies the start of communication by a master device. A dummy acknowledge bit (A) 408 follows the start byte 406. A restart condition (Sr) 410 follows the dummy acknowledge bit (A) 408. The addition of the start byte 406, the dummy acknowledge bit (A) 408 and the restart condition (Sr) provides additional time for slower devices to synchronize and transfer data over bus 120.
The next byte contains the 7-bit address field (ADDR) 412 followed by a 1-bit read/write bit 414. The address field (ADDR) 412 specifies the unique address of the device that is being communicated with or the addressed device. When the read/write bit 414 is logic one (1), this may signify a write operation in which the master may be adapted to operate in receive mode and the slave in transmit mode. When the read/write bit 414 is logic zero (0), this may signify a write operation in which the master may be adapted to operate in transmit mode and the slave in receive mode. The acknowledge (ACK) bit 416 follows the read/write bit 414 and specifies the response from a device that has the corresponding ADDR 412 or the addressed device.
The data byte 318 may represent actual data being communicated followed by a corresponding acknowledgement (ACK) bit 420. Similarly, the data byte 422 may represent actual data being communicated followed by a corresponding acknowledgement (ACK) bit 424. The final data byte 426 may be followed by ACK bit 328. The stop bit (P) 430 which may signify the end of a transaction for a communication session may follow the ACK bit 428. In general, the stop bit (P) 430 follows the last acknowledgement (ACK) corresponding to the last data byte communicated over the bus 120 by a device.
In operation, a slow speed master device may be adapted to send the start condition 404 followed by the start byte 406. A dummy acknowledge bit (A) 408 may be generated and sent to the master device. Upon receipt of the dummy acknowledge bit (A) 408, the master device may generate a restart (Rs) on the SDA line of bus 120 followed by the address of the slave device. The sending of the start condition 404, the start byte 306 and the restart condition (Sr) 410 provides additional time for the slow speed master device to synchronize and communicate over bus 120.
FIG. 5 is a timing diagram 500 illustrating timing parameters for an I2C bus operating in normal mode. Referring to FIG. 5, there is shown various portions of a SDA signal 502 and a SCL signal 504. The following parameters are shown in FIG. 5: tbuf, thd:sta, thd:sta, tlow, thigh, tsu:sta, thd:dat, tsu:dat, tr, tf, and tsu:sto. The parameter tbuf represent the idle time required by the bus after a current transmission and prior to the start of a new transmission. The parameter thd:sta represents a hold time for a start condition. Accordingly, a first clock pulse may be generated after thd:sta. The parameter thd:sta represents a hold time for a restart condition. The parameter tlow represents a low clock period of SCL 504. The parameter thigh represents a high clock period of SCL 504. The parameter tsu:sta represents a setup time for a repeated start condition. The parameter thd:dat represents the hold time for data. The parameter tsu:dat represents a setup time for data. The parameter tr represents a rise time for both SDA 502 and SCL 504. The parameter tf represents a fall time for both SDA 502 and SCL 504. Finally, the parameter tsu:sto represents a setup time for a stop condition.
The following table represents applicable maximum and minimum limits for each of the timing parameters shown in FIG. 5.
ParameterMin. ValueMax. ValueUnittbuf105—μsthd:sta365—μstr:hd:sta210—μstlow105155μsthigh365415μstsu:sta105155μsthd:dat 0—μstsu:dat250—nstr— 1μstf—300μstsu:sto105155μs
Although the I2C bus may be capable of performing peer-to-peer serial communication and may be fairly simple to implement, it is limited to communication speeds of approximately 400 Kbps, with typical operating speeds of about 100 Kbps. Furthermore, even though it lacks common logic signals such as a chip select (CS) and arbitration signals, it is not very adaptable to scaling. In this regard, it may be complex to increase the number of devices that may operate on the bus as well as the distance over which devices can communicate over the bus. Oftentimes, for various reasons, a device may enter an undesired state. However, there are no provisions in the I2C bus that may be utilized to restore such device to a desired state.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.